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Dynamic spectrum access (DSA) supporting opportunistic transmission without extra spectrum bandwidth is attractive for future wireless communication. To facilitate such DSA system, a power-efficient (green) communication processor is needed to support extremely high speed operation on a power-limited mobile device. Traditional general-purpose and digital signal processors are unable to simultaneously...
Currently the DSP applications such as multimedia processing raise the demands to IC designers for more flexibility, higher performance and shorter time-to-market. To solve these problems, this paper proposed a novel reconfigurable operator based IC design methodology for multimedia applications. Four kinds of reconfigurable operators and their logic meanings are introduced in this paper as well as...
The implementation of a recently proposed IP core of an efficient motion estimation co-processor is considered. Some significant functional improvements to the base architecture are proposed, as well as the presentation of a detailed description of the interfacing between the co-processor and the main processing unit of the video encoding system. Then, a performance analysis of two distinct implementations...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Context-based adaptive variable length coding (CAVLC) is a new and important feature of the H.264/AVC. Based on analysis and modification of the conventional run-length coding architecture, a novel high efficiency VLSI architecture for H.264/AVC CAVLC encoding is presented in this paper. An approach called arithmetic table structure is exploited to replace look-up-table ROM for reducing hardware resource...
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