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Although memory is a critical component in general-purpose and application-specific processors, it tends to consume a large amount of power. To alleviate this power dissipation, half-swing memory systems have been proposed which allow memory to be accessed with bitlines that do not swing rail to rail. Unfortunately, half-swing memory systems have additional logic to prevent logic from being written...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
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