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Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate. Check node processing is one bottleneck in NB-LDPC decoding. Various techniques have been proposed to simplify the check node processing. Particularly, the computation complexity can be reduced by employing an iterative forward-backward...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
In this paper, we present an automatic soft IP (Intellectual Property) generation method for high-speed Viterbi decoders. In our scheme, the synthesizable HDL (Hardware Description Language) code for the Viterbi decoder is automatically produced depending on not only the system parameters such as a coding rate but also the hardware architecture for parallel processing. The proposed method is implemented...
The ever changing demands on computational resources has information systems managers looking for solutions that are more flexible. Using a ldquobigger boxrdquo that has more and faster processors and permanent storage or more random access memory (RAM) is not a viable solution as the system usage patterns vary. In order for a system to handle the peak load adequately, it will go underutilized much...
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