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This paper presents a kind of reliable low-leakage cache - RC-Cache, to solve the problem of high soft error rate in low-leakage on-chip caches. The proposed structure combines circuit technique and micro-architecture technique, and can reduce impacts of soft errors on leakage power optimization technique of caches. At circuit level, we improve the soft error immune of SRAM through specially designed...
Modern high-performance processors utilize cache memory systems to tolerate the increasing latency of main memory. Along with IC technology improvement, complicated cache memory systems in processors are very vulnerable to soft errors under severe environment. To deal with multiple soft errors with little impact on hardware overhead and performance, this paper proposes a new cache memory system, in...
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too high. In this paper, we propose Early Write Termination...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs. We illustrate the potential applicability of CACTI-D in...
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