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The soft error rate of memories is increased by high-energy particles as technology shrinks. Single-error correction codes (SEC), scrubbing techniques and interleaving schemes are the most common approaches for protecting memories from soft errors. It is essential to employ analytical models to guide the selection of interleaving distance; relying on rough estimates may lead to unreasonable design...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
In an SRAM array, the systematic inter-die and the random within-die variations in process parameters cause significant number of parametric failures, to degrade process yield in the nanometer technology regime. In this paper, we investigate the interaction between the inter-die and intra-die Vt variations on SRAM read and write failures. To improve robustness of SRAM cell, we propose a closed-loop...
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