The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a new Machine Learning based temperature compensation technique for Ion-Sensitive Field-Effect Transistor (ISFET). The circuit models for various electronic devices like MOSFET are available in commercial Technology Computer Aided Design (TCAD) tools such as LT-SPICE but no built-in model exists for ISFET. Considering SiO2 as the sensing film, an ISFET circuit model was created...
A nano-ampere current reference with temperature compensation operating is presented. The reference current is generated biasing a zero-VT transistor near its Zero-temperature coefficient (ZTC) point. Two versions were implemented in a 180 nm CMOS process. Both are designed using the same thermal compensation principle, but the second version uses an auxiliary circuit to compensate process variation...
This paper presents a self-biased self-cascode MOSFET (SBSCM) voltage reference that can operate with supply voltages as low as 0.45 V while consuming tens of pW. The voltage reference is generated through the self-cascode MOSFET (SCM) using transistors with different threshold voltages and is implemented in a way that the SCM itself composes the bias circuitry. The proposed topology was implemented...
In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to...
Analytical drain current expressions with self-heating effect are presented for undoped polycrystalline thin film transistors (poly-Si TFTs). Temperature dependence of threshold voltage and effective mobility is involved. The expressions are derived on the basis of a first order Taylor expansion and continuous from linear regime to saturation regime. The validity of this model is verified by available...
When considering modern ICs mapped onto nanometer CMOS technologies, increasingly higher power densities and larger power density spatial gradients are well known to be the main source of thermal hot-spots, which in turn may cause huge performance variations, low-energy efficiency, and thus, low reliability. The resulting difficulties in managing temperature have become one of the major challenges...
For the first time, analytical expressions of zero-temperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail. New analytical formulations for the linear and saturation regions of DTMOS transistor operation that make certain the drive current to be temperature independent for the ideal gate voltage are developed. The maximum errors of 0.87% and 2.35% in the...
A new voltage reference with output dependent upon the threshold voltage of an NMOS transistor is introduced. A low temperature coefficient is achieved by using a pn-junction PTAT current generator to compensate for the negative temperature coefficient of the threshold voltage. Implemented in a standard 0.6mum CMOS process with an output of 1.67V, it has a temperature coefficient of 4.9ppm/degC over...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may...
A physical yet analytical phase change memory (PCM) model simultaneously accounting for thermal and electrical conductivities is presented. Due to the physics based nature of the model, the essential temperature from heating and cooling of PCM during operation is instantaneously updated. More importantly, the model can be applied to non-conventional circuit design technique. We show that for the first...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.