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This paper focuses on Negative Bias Temperature Instability (NBTI) awareness to the circuit designer for reliable design of the System-On-a-Chip (SoC) analog circuit. The reliability performance of all matched pair such as current source and differential pair circuits, such as Bandgap Reference, is at the mercy of aging differential. Aging simulation (AgingSim) is mandatory to obtain realistic risk...
It is easy to make mistakes in multilevel flash memories than traditional flash memories, due to the reduced spacing between adjacent threshold voltage, reliability issues turn out to be more critical in multilevel flash memories. But, actual correction only can correct one bit error in flash memory, it cann't meet the need of multilevel flash memory. This paper present a new correction circuitry...
Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector...
Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) due to NBTI is further affected by the initial value of Vth from fabrication-induced process variation (PV). Addressing these challenges in embedded FPGA designs is possible, as FPGA reconfigurablility can be exploited to measure the...
Negative Bias Temperature Instability (NBTI) has become an important reliability concern for nano-scaled Complementary Metal Oxide Semiconductor (CMOS) devices. In this paper, we present an analysis of temperature impact on various sub-processes that contribute to NBTI degradation. We demonstrate our analysis on 90nm industrial design operating in temperature range 25-125?? C. The key temperature...
A power-on-reset circuit of novel simple structure and high reliability is proposed. The circuit has been designed in 0.5 mum bipolar CMOS technology. The simulation was performed with 0.5 mum CSMC process model and Cadence Spectre and the results show that the circuit has a stable and reliable performance. With the differences of supply voltage's ramp rate, temperature and process, the change of...
This paper presents both static and dynamic NBTI Negative Bias Temperature Instability model based on the novel Reaction-Trapping theory. The accuracy of the proposed is greatly improved comparing to the classical Reaction-Diffusion theory, and the results agree well with the experiments over a wide range of temperature. Finally, the NBTI model of FinFETs is demonstrated through SRAM simulation.
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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