The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.