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Dual-Vt technology is effective in leakage reduction and has been implemented in industry EDA tools. However, on-chip temperature is regarded as uniformly distributed over the chip, with a pre-assumed value. This assumption does not hold for designs in the deep sub-micron domain as on-chip temperature variation becomes more and more significant. As a result, treating temperature as a constant will...
This paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and with a characteristic impedance of 75 ohm. The receiver uses self-biased inverters and transmission...
To ensure that an intellectual property (IP) block is validated ahead of its use in an `unknown' system-on-chip (SoC) context, an holistic view of the integration process must be taken. We will focus on the challenges faced in integrating and manufacturing advanced low-power processor based SoC systems, which have dramatically increased the complexity & state space for logical and electrical validation...
3D ICs is a new technology for achieving high density, low power and cost effective designs. As a result of dies being stacked over each other, TSS (Through Silicon tsv Stack) poses a challenge of heat flow and temperature management. A die level thermal analysis tool which can analyze a stacked die configuration, modeling boundary conditions, TSVs and fit into existing SoC design flows is the need...
Rapid changes in SoC power issues has mandated the reconsideration of design methodologies throughout the flow to account for power related effects. This led to the evolution of various design methods to meet power budgets while designing various modern age information systems and computers. In this work, we present a precharge/evaluation based carry generation logic circuit for adders which shows...
A sub-mus wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and separated power lines bypassing rush current to suppress power supply voltage fluctuations. We applied this technique to a heterogeneous dual-core microprocessor fabricated in 90 nm CMOS technology. When wake-up time on the 2M-gate scale circuit was set to 0.24 mus, the supply voltage...
Low power consumption is a key requirement in mobile and other embedded applications. Accurate power estimation during design phase is a key enabler for designing a power optimized SoC. Abstracting accurate power models for complex IPs such as embedded memories is a challenging task. At the same time, the complex modules have a large share in total power consumption of an IC. In this paper we analyze...
We have developed a specialized rapid power-estimation methodology for multimedia applications. This methodology has adequate accuracy for the first design of a complicated SoC. For a multimedia application, we developed three methodologies: an IP-level modeling, a power-level adjustment methodology, and a power accumulation methodology. With these methodologies, the system-level power estimation...
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