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In this paper a reliability analysis and cost optimization method for parallel power converter is proposed. Including a single converter reliability analysis model based on complex network, and a parallel system model to determine the optimum number of single converter X and N based on reliability analysis and cost analysis.
This paper presents a method to implement reliability predictions at an early stage in the design process of power electronic equipment. Detailed information on the component losses are generated using circuit simulation tools. This loss map is applied in 3D thermal simulations of first layout proposals. With the resulting temperature distribution, a reliability prediction can be performed to identify...
To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order Reduction (MOR) techniques to reduce the size of power grids but their focus...
A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide overstress problem in low-voltage CMOS process. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage, which is better than the conventional...
Power domain crossing circuits, also known as internal I/O's, are susceptible to gate oxide damage during charged device model (CDM) events. Circuit-level simulations of internal I/O circuits along with elements representing the package, electro-static discharge (ESD) circuits and the substrate, elucidate the roles of the package, power clamp placement, back-to-back diode placement and the decoupling...
We report on reliability properties of MOCVD PZT ferroelectric capacitors as a function of film thickness. Data is presented for fatigue, thermal depolarization, and imprint. It is important to be able to model these parameters as they can significantly affect the switching polarization, which in turn affects the signal margin of an FRAM circuit. A ferroelectric SPICE model is presented that can be...
A rigorous analysis of Electrostatic Discharge susceptibility of Multi Layer Ceramic (MLC) capacitors is carried out. The impact of ESD stress applied at the connector pins of an electronic control module, protected by utilizing 0603 package MLC capacitors is evaluated. Effectiveness of MLC capacitors for protection of integrated circuits cannot be underestimated, nor should it be assumed as an effective...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
LTCC (low temperature co-fired ceramics) has been become the key technology of packaging for the integrated of RF passive components due to its higher performance of thermal sink, reliability and plays an important role in increasing higher frequency, decreasing the loss, minimize the volume, etc. This paper mainly focuses on the design and fabrication of RF band pass filter by LTCC technology. The...
Real-world realization of RF SoC has been hindered by the lack of high-performance, compact and tunable RF passive devices that are truly CMOS-compatible. This paper presents advances in low-temperature metal MEMS techniques developed to design and fabricate various high-performance RF passives for post-CMOS integration with RF SoC. Constructed with electroplated metal, the RF MEMS passives are suspended...
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