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This paper focused on special requirement of low on-resistance of VDMOS in BCD process. VDMOS structure and its process were studied, and a method for decreasing on-resistance of VDMOS was developed. In this method, a 10 μm deep trapezia ring was formed on the N+ ring of D electrode of VDMOS, and a few more steps were added to ordinary BCD process. Using the method, N-type VDMOS transistor with low...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
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