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A new low voltage power MOSFET concept termed the Junction Enhanced Trench Field Effect Transistor (JETFET) is proposed which combines the advantages of high cell density of trench MOSFET, low gate charge of LDMOS, and low drift region resistance of superjunction MOSFET. The JETFET concept was investigated using 2D process and device TCAD simulation. The feasibility of further improving the Figure...
With emerging issues such as e-mobility and sustainable energy supply, semiconductor power devices again are coming into the focus of academic and industrial research. Low power consumption of these devices requires low on-resistances (RON). With the goal of applying these improvements finally to an IGBT structure, we focus on the optimization of two contributing factors to the RON: the resistance...
A novel lateral super-junction power FINFET (SJ-FINFET) structure suitable for integration is presented to address the challenges associated with sub-100V applications. The proposed lateral SJ-FINFET structure is compatible with advanced SOI-CMOS and FINFET fabrication technologies. It employs a 3D corrugated MOS channel and alternating n/p drift region pillars to achieve a 30% reduction in specific...
High concentration PV systems usually prefer tandem III-V cells to Si cells, due to the much lower conversion efficiency of the latter. We re-examine the efficiency achievable with Si Vertical Multi-Junction (VMJ) cells consisting of series-connected vertical p-n junctions within a single cell. A comprehensive 2D numerical analysis of a Si vertical junction has been performed, over a wide range of...
The design consideration and fabrication of a planar GaAs Schottky barrier diode with cutoff frequency up to 650 GHz is presented in this paper. The theory and design principle was given at the beginning. Then, the key material and geometrical parameters are analyzed using electron behavior analysis and the finite element method. Considering the analyzed results as well as fabrication cost and complexity,...
Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming more challenging and less beneficial. The advanced packaging solutions based on thin silicon carrier are being developed to interconnect integrated circuits and other devices at high densities. A key enabling technology element of the silicon carrier is through silicon via...
Semiconductor (e.g. silicon, germanium) nanowires have gained interest as an attractive platform to fabricate field effect transistors devices because of their reduced short channel effects by comparison to planar devices. The realization of high performance nanowire devices however has been stymied primarily by large source (5) and drain (D) contact resistances. Here we report the fabrication and...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
The recessed gate IGBT has a lower on-state voltage drop compared with the DMOS IGBT, because it doesn't have a JFET region. But due to the electric field concentration in the corner of the gate edge, the breakdown voltage decreases.
This paper considers mechanical stress and strain in a piezoresistive cantilever sensor under surface stress loading, which is the loading condition that occurs in biochemical sensing applications. Finite element simulations examine the piezoresistor sensitivity due to changes in cantilever length, width, and thickness, and piezoresistor size, location, and depth. A few unexpected results are found...
ldquoDevelopment for advanced thermoelectric conversion systemsrdquo supported by the new energy and industrial technology development organization (NEDO) has been successfully completed as one of the Japanese national energy conservation projects. Three types of the cascaded thermoelectric modules operating up to 850 K in high electrode temperature and two types of Bi-Te thermoelectric modules operating...
We report thermoelectric characterization of Bi2-xSbxTe3 (x = 0.5, 1.0, and 1.5) synthesized by a solvothermal method using DMF as solvent. For Bi2Te3, the size of the edge and thickness of the hexagonal nanoplatelets are 200-250 nm and 20-25 nm, respectively. Bi2Te3 nanosheets appear to grow epitaxially from the surface of the Te tubes, which forms in the first step and acts as the template for the...
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