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In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage...
A fully integrated 21 GHz LNA with 10.4 dBm IIP3 is presented in this paper. The LNA is composed of 2 common-source stages and fabricated through standard 0.18 um CMOS technology. By optimizing the gate-bias voltage of NMOS and interstage matching resistance, the linearity is enhanced. Measurement results show that the LNA can get 13.1 dB voltage gain, 5.9 dB NF, less than -10 dB input return loss...
This paper deals with the implementation of a CMOS analog neural network (NN) that has to be integrated in a new kind of optoelectronic measurement system. The aim is to achieve real-time surface recognition using a phase-shift rangefinder and a neural network. NN architecture is a multilayer perceptron (MLP) with two analog input signals provided by the rangefinder, three processing neurons in the...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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