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Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused design blocks. In this paper, we propose techniques and methodologies that utilize abundant external don't-cares that exist in an SoC environment for block optimization. Our symbolic code-statement reachability analysis can extract...
Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) due to NBTI is further affected by the initial value of Vth from fabrication-induced process variation (PV). Addressing these challenges in embedded FPGA designs is possible, as FPGA reconfigurablility can be exploited to measure the...
NCL X circuit is a very efficient way to implement the QDI circuit, which can get all the advantages of the asynchronous circuit, especially the average performance. But the NCL_X circuits suffer from its huge area overhead. To solve this problem, a method for optimizing the complete detection network in the NCL_X circuit has been introduced in this paper. Using this method can dramatically reduced...
A low power circuit design strategy is presented. We believe this methodology can be used to develop fast and inexpensive techniques to aid designers in power optimizations which are generally compute time hungry. The design strategy explored allows for fast sizing of the circuit to get to within 5% of an optimal operating point in terms of energy. Traditional optimization for energy uses time consuming,...
The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained tradeoffs in the power-delay tradeoff curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and precisions. Thus...
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises superiority in exploring the flexibility offered by a design over all previous representation methods. In this work, we illustrate how the SPFD of a particular wire reveals information regarding the number of potential transient...
This paper introduces a framework for the minimization of leakage power consumption of asynchronous circuits via using dual threshold voltages technique. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the circuit. We propose a heuristic method based on quantum genetic algorithm which finds the optimal high and low threshold voltage assignment. Experimental...
The reliability against transient faults poses a significant challenge due to technology scaling trends. Several circuit optimization techniques have been proposed in the literature for preventing soft errors in logic circuits. However, most approaches do not incorporate the effects of other design metrics like delay and power while optimizing the circuit for soft error protection. In this work, we...
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