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Among several optimizations provided by an optimizing compiler, it is a challenge, even for the most expert programmer, to know which compiler optimizations will generate the best target code. The goal of this paper is to describe a case-based reasoning approach that automatically selects a compiler optimization sequence that is able to outperform a well-engineered compiler optimization level in terms...
This paper evaluates various branch-prediction schemes under different cache configurations in terms of performance, power, energy and area on suitably selected biomedical workloads. The benchmark suite used consists of compression, encryption and data-integrity algorithms as well as real implant applications, all executed on realistic biomedical input datasets. Results are used to drive the (micro)architectural...
As the size of NoCs increases, power consumption and fault/variation tolerance have become two of the most crucial problems for system designers. To address these problems, we propose a NoC architecture based on a hierarchy of monitoring agents. By tracing the circuit properties at run time, the agents at different architectural levels are able to monitor and control over the whole NoC platform. This...
Microcoded customized IPs have significantly better performance, yet larger code size, compared to similarly-sized instruction-based processors. Storing wide microcodes on-chip requires wide memory-blocks that occupy a large area and consume high leakage power. Therefore, addressing the code size of microcoded IPs is very important. In this paper, we introduce compression techniques that along with...
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