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In this paper, a leakage current limited SRAM bitcell operating in subthreshold/nearthreshold region is demonstrated in IBM 0.13 μm CMOS process. Proposed bitcell exhibits wide hysteresis effect, making the design less vulnerable to process variation. Its hold margin is 30.2% and 18.9% greater than conventional 6T SRAM and referenced SRAM (at 400 mV). At the same times, the SRAM trip point voltage...
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