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This paper presents a clock and data recovery (CDR) circuit that supports dual data rates of 5.4Gbps and 3.24Gbps for DisplayPort v1.2 sink device. The quarter-rate linear PD in the proposed CDR reduces jitter by enhancing the up and down pulse width. A charge pump (CP) is designed to compensate the different up and down pulse width of the PD and to reduce the current mismatch and power consumption...
The emerging area of body area networks (BAN) imposes challenging requirements on hardware and software to achieve the desired lifetimes for certain devices such as long term medical implants. In this paper, we propose a novel approach to the measurement and characterisation of the energy consumption of BAN devices. The approach uses a low cost energy auditing circuit and addresses the problem of...
A workstation requires a low-power design similar to a typical PC. In this paper we propose several strategies to reduce the power consumption of a workstation. First, we must comprehend the needed dynamic power management for the CPU by using a PWM (Pulse Width Modulation) chip to detect the workload or the current consumption of the CPU. The design then automatically adjusts the CPU voltage and...
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