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In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
In this paper we discuss performance results of a novel real-time closed-loop power amplifier (PA) linearization technique that has originally been proposed by Ahmed and Li. The novel approach performs on-the-fly prediction and measurement of the PA AM/AM and AM/PM non-linearity, stores such non-linear characteristics and calculates their inverse functions in order to pre-distort the base-band amplitude...
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