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A sample/hold (S/H) circuit for a 14 bit 100 MSample/s analog-to-digital converter is implemented and optimized. High performance gain-boosted folded-cascode opamp (GBFCA) and bootstrapped switches are used to maximize SNDR and SFDR of the S/H circuit. An optimal design criterion is developed to find the best solution giving the shortest settling time. After eliminating the slow-settling component...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
In this paper we discuss performance results of a novel real-time closed-loop power amplifier (PA) linearization technique that has originally been proposed by Ahmed and Li. The novel approach performs on-the-fly prediction and measurement of the PA AM/AM and AM/PM non-linearity, stores such non-linear characteristics and calculates their inverse functions in order to pre-distort the base-band amplitude...
We designed and built a novel all-optical re-timing, re-amplifying, and re-shaping (3R) regeneration system based on terahertz optical asymmetric demultiplexers (TOADs) developed in our laboratory. The system is capable of parallel processing multiple wavelengths, a feature which will significantly improve the scalability of current wavelength division multiplexing (WDM) networks. Performance against...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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