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A frequency synthesizer capable of generating all the 14 sub-band carrier frequencies in 3.1~10.6 GHz band for multiband OFDM ultra-wideband (MB-OFDM UWB) transceivers is proposed. It is composed of a phase-locked loop (PLL), two singlesideband (SSB) mixers, and two multiplexers (MUXs). Switched-cascode architecture with switched LC tanks is adopted in the multiplexers to ensure fast switching. A...
This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
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