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A normal way to specify network stack performance for a platform is by indicating the CPU utilization, and the code size (program memory usage) of the stack. This does not take into account performance characterization using different Ethernet packet payload sizes and then measuring the performance against the aggregated bandwidth across the network. This paper presents a realistic method of associating...
Chip-multiprocessors need low cost and high performance communication structure. Network-on-Chip (NOC) is a promising candidate because of its high scalability. In this paper, a hybrid circuit-switched (HCS) NOC is proposed. The HCS NOC uses bufferless switch and pipeline channel to construct the on-chip network. A network interface is also designed to make the HCS NOC AMBA-compatible. Packet setup...
The configurable routing in asynchronous FPGAs accounts for 80-90% of the total area and consumes 80-90% of the total power. This paper presents an asynchronous FPGA that applies two techniques to reduce power consumption. First, the routing is altered to use two-phase logic rather than four-phase logic. Second, enable (acknowledge) signals are voltage scaled such that the overall FPGA performance...
Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip data and protocol transactions. The main problem posed by this communication fabric is the potentially-high and nondeterministic network latency caused by router data buffering and resource arbitration. This paper describes a...
We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput...
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