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In recent years, dramatic growth of mobile data traffic has left the operators no choice but to consider Wi-Fi networks as an economic complementary solution. To achieve this, WLANs require to adopt some of the key features of carrier-grade operators, such as centralized resource management. As an emerging paradigm, Software Defined Networking (SDN) can be used to provide salient centralized network...
Many algorithms for gate size and threshold voltage (VT) optimization have been proposed. The International Symposium of Physical Design (ISPD) contests for discrete gate sizing with wire loads have led to improved algorithms. However, significant changes in cell sizes require re-placement and re-routing which invalidate the wire loads upon which the sizing was performed. In turn, sizing must be re-performed...
Recent papers have demonstrated that graph-based methodologies for supergate design can provide solutions with fewer transistors when compared to the widely used factoring methods. However, there is not enough discussion about the impact of those solutions on physical design, and it is important since the generated supergates have some special topological particularities. In this paper, we perform...
Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel...
In this paper, we propose using software-defined networking technologies for optimal traffic engineering in cellular networks with service chaining. We study the case in which virtual machines are used to support network services and each flow requires multiple network services. To minimize the maximum load of virtual machines and guarantee that the sum rate of admitted flows is large enough, we formulate...
Scan chain timing is increasingly critical to test time and product cost. However, hold buffer insertions (e.g., due to large clock skew) limit scan timing improvement. Dynamic voltage drop (DVD) during scan shift further degrades scan shift timing, inducing “false failures” in silicon. Hence, new optimizations are needed in late stages of implementation when accurate (skew, DVD) information is available...
Multi-NoC (multiple network-on-chip) has demonstrated its advantages in power gating for reducing leakage power. This work presents Chameleon, a novel heterogeneous Multi-NoC design. Chameleon employs a fine-grained power gating algorithm which exploits power saving opportunities at different levels of granularity simultaneously. Integrated with a performance-aware traffic allocation policy, Chameleon...
We develop an algorithm to optimize routing and channel assignment for multi-channel wireless mesh networks. We apply our proposed algorithm to a cognitive radio system using TV white space channels, which has been developed in previous researches. To maximize the capacity and throughput of such multi-channel mesh networks, conventional algorithms separately deal with two problems, the channel assignment...
In this paper we present a concept of a reconfigurable logic toolchain. The specialty of this toolchain is the highly configurable architecture design. The goal is to provide the designer with the ability to suit the architecture of the reconfigurable logic to a specific application domain, for example communication or image processing. Thereby the disadvantages of very flexible, universal structures...
This paper presents an investigation about the ideal composition of cell libraries to be used for digital Application Specific Printed Electronics Circuits (ASPECs). Printed/organic/flexible electronics is becoming more and more important over the last years, and it seems that the industry will continue growing as new possible applications arise, and the existing ones are being improved due to better...
A wireless mesh employing directional antenna, termed DMesh in this paper, can greatly extend coverage and improve spatial reuse of wireless channels. As beaming direction of the antennas changes network topology which in turns affects routing and channel decisions, we address in this work how to jointly optimize topology (in terms of beaming directions of antennas), routing and channel assignment...
In recent years, interconnect issues emerged as major performance challenges for Two-Dimensional-Integrated-Circuits (2D-ICs). In this context, Three-Dimensional-ICs (3D-ICs), which consist of several active layers stacked above each other, offer a very attractive alternative to conventional 2D-ICs. However, 3D-ICs also face many challenges associated with the Power Distribution Network (PDN) design...
Wireless Mesh Networks (WMNS) have emerged in the last years as a cost-efficient alternative to traditional wired access networks. In order to fully exploit the intrinsically scarce resources WMNS possess, the use of dynamic routing has been proposed. We argue instead in favour of separating routing from forwarding (i.e. à la MPLS) and implementing a dynamic load-balancing scheme that forwards incoming...
To maintain a lower re-masking cost, Engineering Change Order (ECO) using pre-placed spare cells for buffer insertion and gate sizing has been shown to be practical for fixing timing violating paths (ECO paths). However, in the previously known best scheme DCP [1, 2], re-routings are done with each path optimized according to its surrounding available spare cells without considering potential exchanges...
Physical synthesis has emerged as one of the most important tools in design closure, which starts with the logic synthesis step and generates a new optimized netlist and its layout for the final signoff process. As stated in [1], “it is a wrapper around traditional place and route, whereby synthesis-based optimization are interwoven with placement and routing.” A traditional physical synthesis tool...
While raising the level of abstraction in design methodologies is uniformly accepted as desirable, raising Design For Test of complex VLSI chips is still challenging for both analysis and implementation. Still, testing logic can be described at the RT-level, and inserting it before synthesis has many advantages, among which the ability to debug testability issues early in the design flow, and leveraging...
ECO re-mapping is a key step in functional ECO tools. It implements a given patch function on a layout database with a limited spare cell resource. Previous ECO re-mapping algorithms are based on existing technology mappers. However, these mappers are not designed to consider the resource limitation and thus the corresponding ECO results are generally not good enough, or even become much worse when...
In recent years, along with the increasing popularity of multi-hop wireless networks, there has been a growing demand in the coupling of these networks to external ones such as the Internet. As traffic destined for external networks increases, special attention is required not only in gateway selection, but also in optimized routing and scheduling in order to maximize the network performance. In this...
In this paper, we propose a new intersection-based geographical routing protocol, called delay tolerant routing protocol (DTRP) that adapts to the changes in the local topology within city environments. DTRP is based on an effective selection of road intersections through which a packet must pass to reach the gateway to the Internet. The selection, in such delay tolerant VANETs, is made in a way that...
The main design challenge in wireless sensor networks is to achieve satisfactory network lifetimes under scarce energy resources available at the nodes. In this paper we present an optimization framework for maximizing lifetime of a network in which opportunistic routing together with random linear network coding is used. We propose a scheme in which each node attempts to receive transmissions from...
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