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Evolutionary algorithms are another option for combinational synthesis because they allow for the generation of hardware structures that cannot be obtained with other techniques. This paper shows a parallel genetic programming (PGP) boolean synthesis implementation based on a low cost cluster of an embedded platform called SIE, based on a 32-bit processor and a Spartan-3 FPGA. Some tasks of the PGP...
The evolution to Manycore platforms is real, both in the High-Performance Computing domain and in embedded systems. If we start with ten or more cores, we can see the evolution to many tens of cores and to platforms with 100 or more occurring in the next few years. These platforms are heterogeneous, homogeneous, or a mixture of subsystems of both types, both relatively generic and quite application-specific...
As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. The feature allows multiple...
Fast and efficient accumulation arithmetic circuits are critical for a broad range of scientific and embedded system applications. High throughput accumulation circuits are typically hand designed for specific vector lengths requiring the circuit to be modified when the lengths are changed. In this work we present a new design approach that can achieve low latency and near optimal throughput for input...
Operating in critical environments is an extremely desired feature for fault-tolerant embedded systems. In addition, due to design test and validation complexity of these systems, faster and easier development methods are needed. Evolvable Hardware (EHW) is a development technique that, using reconfigurable hardware, builds systems that reconfiguration part is under the control of an Evolutionary...
This paper introduces an approach for the safe design and modeling of dynamically reconfigurable FPGA based Systems-on-Chip. This approach is carried out in a design framework, GASPARD2, dedicated to high-performance embedded systems modeling using the OMG standard profile UML/MARTE. Information employed by the reconfiguration mechanism is identified to be extracted from MARTE models in order to synthesize...
The SoCKET project (SoC1 toolKit for critical Embedded sysTems)2 gathers industrial and academic partners to address the issue of design methodologies for critical embedded systems. They work towards the definition of a “seamless” design flow which integrates qualification and certification, from the system level to integrated circuits and to software. This paper sketches such a design flow and the...
Chaotic encryption schemes are believed to provide a greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details using FPGA technology are provided. Logistic map is the simplest chaotic system and has a high potential to be used to design a stream cipher for real-time embedded systems. The cipher uses...
This paper presents Embedded System Environment (ESE), which is a comprehensive set of tools for supporting a model-based design methodology for multi-processor embedded systems. It consists of two parts: ESE Front-End and ESE BackEnd. ESE Front-End provides automatic generation of SystemC transaction level models (TLMs) from graphical capture of system platform and application C/C++ code. ESE generated...
Gigabit Ethernet technology has become the mainstream now, and many applications also require real-time transmission of high-speed data, so how to realize gigabit ethernet interface becomes a new topic. This paper proposes and implements an embedded system based on RTL8169SC and FPGA. PCI interface logic is embedded in FPGA, therefore the single FPGA includes both user logic and interface logic.The...
This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control...
Nowadays, the Network-on-Chip (NoC) paradigm has become more and more popular for building an on-chip communication infrastructure. Like in every traditional network, debugging and performance monitoring are also very important issues in NoC-based systems. Unfortunately, the design process of monitoring hardware is a time consuming activity. The work presented in this paper is based on a high level...
The embedded systems for which both hardware and software are rapidly advancing and expanding, there is a growing need to be able to comprehensively and quantitatively estimate system performance at an early stage in the design process, especially multi-core based SoC. But it can be difficult to estimate system performance of actual target by employing only simple estimation methods. By using ESL...
With the increasing hardware capacity, embedded systems are becoming more and more complex, requiring new design techniques/methods. UML allows higher abstraction level system modeling and MDA techniques allow automatic code generation. In this paper we propose a UML/MDA approach to rapidly model and automatically generate MPSoPC systems. Our approach uses MARTE as extension mechanism in order to...
Embedded systems designers frequently avoid using floating-point computation because it is too costly to include a floating-point unit (FPU) in an embedded processor. However, the performance of software floating-point libraries can be lacking. Therefore we propose a fractured floating point unit (FFPU)-a hybrid solution using a mix of custom hardware instructions and software code. An FFPU is designed...
Although the use of floating point hardware in FPGAs has long been considered unfeasible or relegated to use only in expensive devices and platforms, this is no longer the case. This paper describes fully-fledged implementations of single-precision floating point units for a MIPS processor architecture implementation. These coprocessors take as little room as 6% of a medium-sized FPGA, while the processor...
Field Programmable Gate Arrays (FPGAs) are increasingly being used for many systems and efficient System-on-a-Chip (SOC) designs. Hence, dynamic partial self reconfiguration (DPSR) of the FPGA can be regarded as one of essentials of making hardware flexible and achieving power efficiency and optimizing area too. This paper presents an approach for dynamic partial self-reconfiguration that enables...
In this paper, a novel approach for digital image chaotic communication via FPGA embedded Ethernet transmission is proposed. Based on Euler algorithm and variable ratio expansion transformation, by C language programming under the Linux operating system, the continuous time 8-scroll Chua system is converted to the discrete sequence used to encrypt and decrypt image on the FPGA-based platform. According...
The appearance of the new MPEG-4 standard offers opportunities for real-time implementations of MPEG-4 encoders suitable for a wide range of applications, including video conferencing, digital storage media, television broadcasting, Internet streaming, and communication. With the rapid development of FPGA, SOPC has been paid great attentions in the area of image and video processing in recent years...
Application-Specific Instruction set Processor (ASIP) has become an increasingly popular platform for embedded systems because of its high performance and flexibility. Energy efficiency is critical for portable and embedded devices, and should be addressed separately from performance consideration. The hardware extension in ASIPs can speed-up program execution, but also incurs area overhead and static...
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