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This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
A low power reconfigurable DCT architecture is proposed, which can be run at three transform precision levels for different demands. Using the character of energy distribution of the DCT matrix after 2D DCT operation, we selected the best DCT bases which achieve considerable power reduction in DCT operation with minimum image quality degradation. The reconfigurable architecture can achieve power saving...
The next generation of wireless networks (4G) will use OFDMA (Orthogonal Frequency Division Multiple Access) in the reverse link. In OFDMA, the reverse link resources assigned to a user are called tiles each of which consists of a subset of consecutive subcarriers. Since at most one user is assigned to each of these tiles then reverse link transmissions within a sector are orthogonal. However, the...
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