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High performance embedded applications are developed using system-on-chips (SoCs) which in turn include silicon intensive, integrated application processors. These SoCs integrate multi-core processor (i.e., ARM Cortex9 or A15) with variety of memory interface controllers, communication interface controllers and special purpose accelerators. Traditionally bus matrix is used for integrating these intellectual...
New and advanced simulations and sensors produce data sets whose increasing complexity makes them difficult to visualize and comprehend directly. To cope with this problem, we can detect and extract significant features in the data and use them as the basis for further analysis. Topological methods are useful in this context because they provide us with robust and generalized feature definitions....
Homogeneous manycore processors are emerging in broad application areas, including those with timing requirements, such as real-time and embedded applications. Typically, these processors employ Network-on-Chip (NoC) as the communication infrastructure and core-level redundancy is often used as an effective approach to improve the yield of manycore chips. For a given application's task graph and a...
Current packet processing systems only aim at producing high throughput without considering packet latency reduction. For many real-time embedded network applications, it is essential that the processing time not exceed a given threshold. In this paper, we propose LATA, a LAtency and Throughput-Aware packet processing system for multicore architectures. Based on parallel pipeline core topology, LATA...
In recent years, due to efficient topological properties, e.g., logarithmic diameter, simple routing etc, the multi mesh of trees (MMT) topology is center of attraction for researches. The multi-mesh of trees is a hybrid network of the multi-mesh (MM) and the mesh of trees (MoT) with n ?? n mesh of trees consists of n2 processors. Prefix-computation on multi-mesh (MM) topology have been proposed with...
This paper proposes a new process mapping scheme called adjacency-based mapping (AM) for irregular cluster systems assuming that the two-dimensional mesh process topology is specified as an interprocess communication pattern. The proposed AM tries to map neighboring processes in virtual process topology to adjacent processors in physical processor topology. Simulation study shows that the proposed...
The way of on-board digital signal processing based on FPGA is studied. It contains requirement analysis of the on-board processing functional specifications, an on-board real-time digital signal processing system is designed with radiation tolerant FPGA. The design takes full advantage of the massively parallel architecture of the FPGA logic slices to achieve real-time processing at a high data rate,...
In this paper, we present an FPGA prototype implementation of a rotator-on-chip (RoC), a simple and scalable novel network-on-chip (NoC) based on the token-ring concept. The reported prototype design is generic with respect to the number of nodes and data channels. We report synthesis results showing a O(N log N) area complexity, where N represents the number of nodes, with a quasi-linear aggregate...
This paper addresses the problem of how to adapt an algorithm designed for fixed topology networks to produce the intended results, when run in a network whose topology changes dynamically, in spite of encountering topological changes during its execution. We present a simple and unified procedure, called a reset procedure, which, when combined with the static algorithm, achieves this adaptation....
Let d = d(n) be the minimum d such that for every sequence of n subsets F1, F2, . . . , Fn of {1, 2, . . . , n} there exist n points P1, P2, . . . , Pn and n hyperplanes H1, H2 .... , Hn in Rd such that Pj lies in the positive side of Hi iff j ∈ Fi. Then n/32 ≤ d(n) ≤ (1/2 + 0(1)) ?? n. This implies that the probabilistic unbounded-error 2-way complexity of almost all the Boolean functions of 2p variables...
We give an algorithm to construct a cell decomposition of Rd, including adjacency information, defined by any given set of rational polynomials in d variables. The algorithm runs in single exponential parallel time, and in NC for fixed d. The algorithm extends a recent algorithm of Ben-Or, Kozen, and Reif for deciding the theory of real closed fields.
Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout...
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph. We give an algorithm that produces VLSI layouts for classes of graphs that have good separator theorems. We...
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