Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Modeling and simulation has received significant attention over the years for its ability to understand and transform real world systems. With the increasing of complexity and scale of the simulated systems, more computational power is required. Parallel discrete event simulation(PDES) is an important technology to integrate parallel computing into modeling and simulation. Time synchronization algorithm...
We evaluate the applicability of many-core architectures for the simulation of networks on chips (NoC). Compared to the well established shared memory multi-core architectures, many-core architectures significantly differ not only in the number of processing elements but also in the on-chip communication architecture, the memory subsystem, and the computational performance of an individual core. Proven...
We evaluate the applicability of many-core architectures for the simulation of networks on chips (NoC). Compared to the well established shared memory multi-core architectures, many-core architectures significantly differ not only in the number of processing elements but also in the on-chip communication architecture, the memory subsystem, and the computational performance of an individual core. Proven...
As the system complexity increases, the simulation performance becomes one of the most important issues in virtual prototyping. Parallel simulation is a fascinating technique for high-speed simulation utilizing state of the art multi-core processors on a host workstation, but the efficiency of the parallel simulation is low because of the synchronization and communication overhead and unbalanced workloads...
Heterogeneous System Architecture (HSA) is an open industry standard designed to support a large variety of data-parallel and task-parallel programming models. Currently, most of HSA hardware and software components are still in development. It is helpful to provide various heterogeneous simulation environments for HSA developers in developing HSA software stacks. This paper presents the design of...
Simulation is an important method to evaluate future computer systems. However, the increasing complexity of the target systems has made the development of simulators very difficult. Furthermore, detailed simulation of large-scale parallel architecture is so slow that full evaluation of real application becomes a great challenge. This paper presents SimICT, a fast and flexible simulation framework...
A common practice for reducing synchronization overheads in parallel simulation of a large-scale cluster is to relax synchronization with lengthened synchronous steps. However, as a side effect, simulation accuracy degrades considerably. This paper proposes a novel mechanism that keeps the running speeds of different nodes consistent by synchronizing logical clocks with the wall clock periodically...
Parallel simulations focus on conservative or optimistic algorithms to guarantee state consistency and causal order of messages between logical processes (LPs). It is usually hard for application domain users to develop complicated models for parallel simulations. For simplicity in large-scale artificial society, a modified DEVS component model is advocated in time-stepped parallel simulation with...
This paper introduces PartitionSim, a parallel simulator for future thousand-core processors. The purpose of PartitionSim is to improve the simulation performance of many-core architectures at the expense of little accuracy sacrifice. To achieve this goal, we propose a novel technique: timing partition. Timing partition is based on such an observation: in a target system, interacting components communicate...
To improve the time performance of SMP2 Simulation under Service Oriented Architecture, a hybrid time synchronization method is promoted. The method would reduce the redundancy message exchange via specifying different time advance policy to different SMP2 simulation node. An interaction graph model is introduced based on SMP2 model composition and schedule and the parallelity evaluating algorithm...
In this paper, we study general K-queue first-in-first-out homogeneous fork/join queueing (HFJ) systems for any K ≥ 2. We simulate and analyze an upper-bound for the mean response time that we denote by T[K]. The upper-bound uses a relatively tiny-scale system to predict the performance of a huge-scale system. It is evaluated for 10-million queues on a regular HP-PC with Intel i7-860 for three different...
Increasing complexity of multicore embedded systems makes careful construction of virtual prototyping system crucial to shorten design turnaround time due to the growing demand of simulation time. Parallel simulation aims to accelerate the simulation speed by running component simulators concurrently. But extra overhead of communication and synchronization between simulators may overshadow the benefits...
Current trends signal an imminent crisis in the simulation of future CMPs (Chip Multiprocessors). Future micro-architectures will offer more and more thread contexts to execute parallel programs, but the execution speed of each thread will not improve at the same pace. CMPs with 10's or even 100's of cores are envisioned. Simulating these future CMP sefficiently without compromising accuracy is a...
This paper describes the design and application of an execution-driven parallel simulator for predicting performance of Large-Scale Parallel Computers. The simulator can be used in hardware validation and software development for large-scale parallel computers. It simulates processors of each node, network components and disk I/O components. To illustrate the capabilities of our simulator, we describe...
We present a set of modeling constructs accompanied by a high performance simulation kernel for accuracy adaptive transaction level models. In contrast to traditional, fixed accuracy TLMs, accuracy of adaptive TLMs can be changed during simulation to the level which is most suitable for a given use case and scenario. Ad-hoc development of adaptive models can result in complex models, and the implementation...
Computer clusters are a very cost-effective approach for high performance computing, but simulating a complete cluster is still an open research problem. The obvious approach - to parallelize individual node simulators - is complex and slow. Combining individual parallel simulators implies synchronizing their progress of time. This can be accomplished with a variety of parallel discrete event simulation...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.