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This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
One method of model-based compensator design for linear systems consists of two stages: state feedback design and observer design. A key issue in recent work in multivariable synthesis involves selecting the observer (state feedback) gain so that the final Loop transfer function is the same as the state feedback (observer) loop transfer function. This is called Loop Transfer Recovery (LTR)(1,4,6,7)...
A design method that makes a trade-off between noise reduction and stability requirements is suggested in the case when the process is modelled as a time invariant linear stable plant. The suggested controller is obtained by modifying the well known LQG-controller. Only the SISO-case is treated here. We give analytical expressions on how stability margins can be improved and how the stochastic properties...
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