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To effectively reduce output ripple of switched-capacitor DC-DC converters which generate variable output voltages, a novel feedback control scheme is presented. The proposed scheme uses pulse density and width modulation (PDWM) to reduce the output ripple with low output voltage. The prototype chip was implemented using 65nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V...
In this paper, counter-based pulse-width-modulated (PFM) control according to the output voltage ripple using a one-comparator scheme without any analogue-to-digital converter (ADC) used is presented herein, which is realized based on the field programmable gate arrays (FPGA) and applied to DC-DC converters. However, too small or distorted output ripple limits its performance. Consequently, a positive-sloped...
A single-inductor dual-output boost converter reported in works either in discontinuous conduction mode or in pseudo-continuous conduction mode and requires separate controllers. As each controller regulates the output in time-multiplexed manner, it is difficult to extend the number of outputs and power capacity. The converter reported in solves these limitations by adopting comparator-controlled...
The paper introduces a new scheme to track the rotor position of an induction motor. The scheme uses the measurement of current derivatives during null switching vectors of a standard PWM scheme and reduces the minimum pulse widths required to allow high frequency switching oscillations to die down. The motor current distortion is therefore also reduced. The method uses H-Bridges connected in series...
This paper deals with a new topology for a multi - level - converter without a multi - winding input transformer. By means of this topology, converter with an increased number of voltage steps can be easily realised. The number of valves is smaller than that of actual techniques. Additionally the paper compares the multi - level - PWM with the optimised pulse sequences.
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