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The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area...
This paper proposes a new VLSI architecture for decoding Reed-Solomon codes with a modified Berlekamp-Massey algorithm. By employing t-folded architecture, we achieve the highest throughput and the resource utilization efficiency without degrading performance on critical path delay. More interestingly, on the basis of the proposed architecture, further complexity benefit can be realized by sharing...
Decimal multiplication is an integral part of financial, commercial, and Internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based ona novel RPS algorithm. This design uses n single...
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