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An extremely low energy per operation, single cycle 32 bit/word, 128 kb SRAM is fabricated in 90 nm CMOS. In the 850 MHz boost mode, total energy consumption is 8.4 pJ/access. This reduces to 3.6 pJ/access in the normal 480 MHz mode and bottoms out at a very aggressive 2.7 pJ/access in the 240 MHz low power mode. Several techniques were combined to obtain these performance numbers. Short buffered...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
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