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We describe the design, implementation, and experimental evaluation of a clock recovery algorithm suitable for synchronization over a packet-based metro-area network (MAN) using the Precision Time Protocol (PTP). The algorithm consists of a packet-based phase error estimator and a phase-locked loop (PLL). The loop is augmented with a step detector that detects discontinuities in the packet arrival...
A phase detector for timing recovery phase locked loops with an accuracy better than 0.5 % for input frequencies up to 100 MHz is presented. The core of the phase detector consists of two modified Gilbert cells combined so that the offset in their output current is cancelled. This core is expanded with logic circuitry at the input to make the phase detector suitable for timing recovery applications...
This paper describes a novel single-chip design of a clock recovery and data retiming circuit. The chip, when used on the receiving end of a serial data link, recovers a clock from NRZ random data transmitted at any bit rate between 1 and 50 mb/s and synchronizes the clock with the data stream. The chip has been fabricated using a 1.75 micron twin-tub CMOS process and is packaged in a 20 pin plastic...
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