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This paper deals with the management of a SoC-based current controller using an efficient Real-Time Operating System (RTOS). To accelerate the services of this operating system, a Real-Time Unit (RTU) was developed in VHDL and associated to the RTOS. It consists in hardware operating system that moves the scheduling and communication process from software RTOS to hardware. Thus, a significant acceleration...
The path analysis and trajectory planning of composite elbow winding machine is presented with the post-process technology. With the PMAC as the motion controller and the Windows operating system as the development platform, the real-time download of large capacity numerical control program is realized with the dual-port RAM communication. The real-time dynamic control process of elbow winding is...
This paper describes the design of a highly customizable hardware packet filtering firewall to be embedded on a network gateway. This firewall has the ability to process the data packets based on source and destination TCP/UDP port number, source and destination IPaddress range, source MAC address and combination of source IP address, and destination port number. It is capable of accepting configuration...
This paper describes the architecture of the functional electrical stimulation systems developed in the context of the TIME European project. Contributions are the definition of a generic FES architecture and the specialization of this architecture, depending on the applicative context, by the deployment, the programming and the control of hardware units, notably stimulation ones. This specialization...
Real-time image processing demands much more processing power than a conventional processor can deliver. As a result hardware acceleration became necessary to augments processors with application-specific coprocessors. Due to the limited resources on FPGA and nature of some sequential algorithms, it is difficult to depend entirely on slice resources. In this research, we implemented a multiprocessor...
In this paper, we introduce the design of an IP processor core code-named CUSPARC for Cairo university SPARC processor. This core is a 32 bit pipelined processor that conforms to SPARC v8 ISA. It is complete with 4 register windows, I and D caches, SRAM and flash memory controller, resolution hardware for the data and branch hazards, interrupts and exception handling, instructions to support I/O transfers,...
When facing the emergencies, to achieve the whole day real-time scanning services on targets, we propose a program with integration of visible and infrared imagers. A novel airborne low-altitude monitoring system is designed. it helps operators to detect targets accurately. Experiments show that the design is feasible and the system is practical, reliable, and easy to operate, displays Chinese characters,...
We recently implement a real time software Digital Scan Converter algorithm for sector B-mode ultrasound based on a PC with 1.6G dual-core CPU and 1GB RAM. Several measures are taken to increase the speed, such as lookup table (LUT), integer arithmetic, section interpolation, double-buffer for incoming data and multi-threaded coding. The algorithm programmed with C++ runs on Linux operating system...
In this paper, an Ethernet data acquisition and transmission unit designed for general purpose information exchange between different channels has been proposed. In hardware, it is composed of only one chip and multiple interfaces which result to easy design and excellent stability; in software, the ??C/OS-II, an embedded Real Time Operation System(RTOS), is applied and runs on the microcontroller,...
This article introduces a kind of Intelligent PCI CAN bus card based on the dual-port RAM(DRAM). First, the whole scheme of the system is presented, then the designs of the hardware and software of Intelligent PCI card Based on CAN bus are expatiated and focused on the structure of DRAM, the general mechanism for the data exchange between the HOST and DEVICE and the communication in I/O and message...
A novel Spectral Signal Processing System (SSPS), which uses a high-speed floating-point digital signal processor (DSP) as its central processor, is presented in this paper. This system is used in Fourier transform infrared (FTIR) spectrometer. The basic working principle of SSPS is briefly introduced. The design solutions and the architecture of hardware platform, including signal processing block,...
This paper presents a low cost FPGA based solution for a real-time moving object tracking system. A specialized architecture is presented based on a soft RISC processor capable of running kernel based mean shift tracking algorithm. The system includes a frame grabber unit that stores the video frame in DDR RAM using direct memory access, a video display unit to monitor the tracking statistics and...
Distributed real-time applications implement distributed applications with timeliness requirements. Such systems require a deterministic communication medium with bounded communication delays. Ethernet is a widely used commodity network with many appliances and network components and represents a natural fit for real-time application; unfortunately, standard Ethernet provides no bounded communication...
A hardware and software platform based on ARM (advanced RISC machines) is designed to meet the requisition of reliability and rapidity in line selection. ARM processor LPC2214 with low power loss acts as the controlling center of the platform. The software algorithm called integrated criterion combines several line detection methods to improve adaptability of line selection. The advantages of ARM,...
The problem of detection of control flow errors in software has been studied extensively in literature and many detection techniques have been proposed. These techniques typically have high memory and performance overheads and hence are unusable for real-time embedded systems which have tight memory and performance budgets. This paper presents two algorithms by which the overheads associated with...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
The paper addresses the problem of creating a comprehensive fault injection environment, which integrates and improves various simulation and supplementary functions. This is illustrated with experimental results.
This paper presents a novel method of contour reconstruction from dexel data solving the shape anomalies for the complex geometry in virtual sculpting. Grouping and traversing processes are developed to find connectivity between dexels along every two adjacent rays. After traveling through all the rays on one slice, sub-boundaries are connected into full boundaries which are desired contours. The...
We have developed a browsing tool for visualizing information about geographic surfaces using map-based augmented reality (AR). Map-based AR technology enables virtual objects to be overlaid on an actual map, creating a tangible user interface. In map-based AR applications, a virtual lens pointer is often used for object selection. However, this type of interaction is difficult when there are many...
With the wide use of PROFIBUS-DP and industrial Ethernet, an effective integration solution of the two networks is significant to solve the problem of incompatibility between them. Based on the analysis of current integration methods using PLC, PC/PG or Link, a new class 1 master link based integration of PROFIBUS-DP systems into industrial Ethernet systems is proposed. Comparatively, especially for...
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