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SCMOS is a low cost, high capacity, high speed, high yield, and power saving VLSI device platform technology for microelectronics chips and modules. Benefits include: (1) Uses the complementary Low threshold Schottky Barrier Diodes (LtSBD or simply SBD). (2) Integrated the SBD and CMOS transistor as basic circuit elements for Analog, Logic, and Memory (ALM) macros. (3) Single power supply chip. Circuits...
This paper addresses performance and reliability issues in a 5T SRAM cell, and introduces a low power, reliable and high performance design in 65nm technology, which can be used as cache memory in processors and in low-power portable devices. The proposed SRAM cell features ~13% area reduction compared to a typical 6T cell. In addition, it features a biasing ground line, VSSM, which is charged by...
A SRAM cell must meet stringent requirements for operation in the sub-micron/nano ranges. A nine transistor (9T) cell at a 32 nm feature size in CMOS is proposed to accomplish improvements in stability, power dissipation and performance compared with previous designs for low-power memory operation. Initially, this paper presents the optimal transistor sizing for this 9T SRAM cell considering stability,...
This paper describes a novel area-efficient and full current-mode dual-port (DP) SRAM. It greatly reduced the area consumption of the DP-SRAM by using single-port (SP)-cell instead of 8T-DP-cell. Based on the full current-mode techniques for read/write operation, it also achieved low power consumption. A 1K times 8 proposed DP-SRAM is designed based on 0.18 mum CMOS technology. Its area is only 1...
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