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Virtual Environments have become a compelling tool for various applications beyond gaming and Virtual Worlds, for example for education, collaborative engineering, or simulation and visualization. In the emerging field of smart environments, like Smart Cities and Smart Factories for industry or agriculture, a digital counterpart of a real world site, driven by hundreds of Internet of Things (IoT)...
This paper proposes low-power design of the Gaussian-Minimum Shift-Keying (GMSK) demodulator using baseband quadrature signals. High-level architecture of this demodulator incorporates CO-ordinate Rotation-DIgital Computer (CORDIC) engine to accept the in-phase and quadrature components from received GMSK signal to generate phase angle and magnitude of the GMSK signal vector at half the sampling frequency...
Carrying out network monitoring tasks remains a continuous challenge, partially because the line rate reaches and exceeds 100 Gbit/s. Besides the increasing data rate, the advent of programmable networks necessitates efficient solutions for supporting packet processing tasks in an adaptive way. Introducing a modification of a protocol or any new protocol in such a flexible infrastructure implies a...
Hadoop is the de facto engine that drives current cloud computing practice. Current Hadoop architecture suffers from single point of failure problems: its job management lacks of fault tolerance. If a job management fails, even if its tasks remains still active on cloud nodes, this job loses all state information and has to restart from scratch. In this work, we propose a distributed MapReduce engine...
Self-awareness and self-expression are promising architectural concepts for embedded systems to be equipped with to match them with dedicated application scenarios and constraints in the avionic and space-flight industry. Typically, these systems operate in largely undefined environments and are not reachable after deployment for a long time or even never ever again. This paper introduces a reference...
Parallel simulations focus on conservative or optimistic algorithms to guarantee state consistency and causal order of messages between logical processes (LPs). It is usually hard for application domain users to develop complicated models for parallel simulations. For simplicity in large-scale artificial society, a modified DEVS component model is advocated in time-stepped parallel simulation with...
Although large scale high performance computing today typically relies on message passing, shared memory can offer significant advantages, as the overhead associated with MPI is completely avoided. In this way, we have developed an FPGA-based Shared Memory Engine that allows to forward memory transactions, like loads and stores, to remote memory locations in large clusters, thus providing a single...
In interactive multi-user virtual environments, the computation and bandwidth required to perform real-time simulation increases quadratically with the number of users. Handling communication, storage and computation resources on the same machine hinders scalability. This paper presents a system architecture abiding to the constraints of the REpresentational State Transfer (REST) architectural style...
Heterogeneous Computing is becoming an important technology trend in HPC, where more and more heterogeneous processors are used. However, in traditional node architecture, heterogeneous processors are always used as coprocessors. Such usage increases the communication latency between heterogeneous processors and prevents the node from achieving high density. With the purpose of improving communication...
New design methodologies and modeling frameworks are required to provide a solution for integrating legacy code and IP models in order to be accepted in the industry. To tackle this problem, we introduce the concept of wrappers in the context of a formal heterogeneous embedded system modeling framework. The formalism is based on the language-independent concept of models of computation. Wrappers enable...
In this paper, an Application Specific Instruction-set Processor (ASIP) architecture to perform all OFDM synchronization tasks is proposed. While applicable to many OFDM systems, the proposed architecture is tested on Long Term Evolution (LTE Rel. 8) and WiMAX 802.16e systems. The synchronization tasks include, but not limited to symbol timing, fine carrier frequency offset (CFO) estimation, coarse...
As the safety of motor vehicle is taken more and more seriously, the real-time events in the automotive electronics is more important. The control of engine and power train is the core of automotive electronics, and also the domain which demand the real-time quite seriously. This paper proposes a method which can decode the engine position signal. This method is under AUTOSAR frame, based on the MPC5554...
Simulation-based study plays important roles in robotic systems development and Hardware-in-the-Loop Simulation is an increasingly popular engineering tool, because it maintain effectively a balance between two competing demand such as well-designed and thoroughly tested system. This technique reduces the need to develop models for existing hardware and increases the accuracy of the overall system...
This paper introduces a modular software platform and the respective synchronization mechanisms that support services with flexible multimodal user interfaces (UI). The platform is based on Java technology for the service logic and XML-based description languages such as SVG and VoiceXML for UI definition. A Sensor Data Manager allows including input from device sensors such as accelerometers. First...
For a high-performance parallel implementation of many scientific algorithms, efficient realizations of combining communication patterns like reduce or all-reduce are important. Especially on the Cell Broadband Engine a low latency realization of such operations is not obvious. So in this paper several algorithms for implementing reductions are discussed and efficient implementations on the Cell are...
MapReduce is a programming model that supports distributed and parallel processing for large-scale data-intensive applications such as machine learning, data mining, and scientific simulation. Hadoop is an open-source implementation of the MapReduce programming model. Hadoop is used by many companies including Yahoo!, Amazon, and Facebook to perform various data mining on large-scale data sets such...
The problem of inverting matrices is one that occurs in some problems of practical importance. This paper introduces and evaluates the block algorithm for high performance matrix inversion on the Cell Broadband Engine (Cell/B.E.) processor. The Cell/B.E. is a heterogeneous multi-core processor on a single-chip jointly developed by Sony, Toshiba and IBM, which has a very high speed of the single precision...
A new generation network is requested to accommodate a enormous amount of nodes with high diversity and a wide variety of traffic and applications. To achieve higher scalability, adaptability, and robustness than ever before, we propose new network architecture in this paper. The architecture consists of the physical network layer, service overlay network layer, and common network layer mediating...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
The imaging laser radar is fine measure equipment for TAN with the ability to get the high precision 3D terrain. A 3D terrain matching processor was needed to be designed for the specifical application. In this paper, base on the specialty of the imaging laser radar, the3D terrain matching processor was designed, with scheme of DSP+FPGA calculating engine, multi-level memory system, flexible parallel...
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