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Convolutional Neural Networks are being studied to provide features such as real time image recognition. One of the key operations to support HW implementations of this type of network is the multiplication. Despite the high number of operations required by Convolutional Neural Networks, they became feasible in the past years due the high availability of computing power, present on devices such as...
A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
This paper presents an architecture of system Verilog assertions (SVA) synthesis compiler, which translates the un-synthesizable System Verilog assertions, into synthesizable equivalent Verilog modules, in order to convert them to digital hardware circuits, used to watch how the running design performs. The proposed architecture is based on two main rules: "Simple compiler structure" and...
The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience...
Multiplication of floating point numbers found extensive use in DSP applications involving huge range. The critical part in floating point multiplication is the multiplication of mantissas which uses 24∗24 bit integer multiplier for single precision floating point numbers. The speed of the system can be enhanced by improving the speed of multiplication. In this paper a 24 bit Vedic multiplier has...
Obfuscation is a technique which makes design less intelligible in order to prevent or increase reverse engineering effort. In this paper, a new approach to hardware obfuscation by inserting constant value generators (CVGs) is proposed. A CVG is a circuit that generates the same fixed logic value but will not be minimized by the synthesizer. CVGs can be used to create new logic primitives, embed watermarks...
In this work, two approaches to realize a finite impulse response (FIR) filter using residue number system (RNS) are proposed. The proposed implementations take advantage of shift and add approach offered by the chosen moduli set. Both the architecture were implemented using gate level Verilog HDL and are synthesized using Cadence RTL compiler in UMC 90 nm technology. The performance of the filters...
Many arithmetic circuits utilize multioperand addition, usually using carry-save adders (CSA) trees. Automatic generation of custom VHDL models for these CSA trees, allows the designer to perform a time efficient design space exploration. Although, the CSA trees are heavily utilized in modern digital circuits, there is no tool, accessible from the web, to generate the HDL description of such multioperand...
SystemVerilog is a hardware design and verification language (HDVL) that combines the features of several domain-specific languages for digital hardware design and verification with a general purpose object-oriented programming language. The paper discusses the functional and performance requirements of each domain, and the history of why particular language design choices were made. SystemVerilog...
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