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We present a synchronization algorithm that is able to let the nodes in a sensor network perform a certain task at a given point in time. In contrast to other time synchronization algorithms we do not provide a global time basis that is shared on all nodes. Instead, any node in the network can spontaneously initiate a process that allows the synchronous execution of arbitrary tasks. We show that our...
Traditional operating systems differentiate between threads, which are managed by the kernel scheduler, and interrupt handlers, which are scheduled by the hardware. This approach is not only asymmetrical in its nature, but also introduces problems relevant to real-time systems because low-priority interrupt handlers can interrupt high-priority threads. We propose to internally design all threads as...
Computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coherence protocols for these platforms is too complex and expensive. As a substitute, we propose a synchronization based cache coherence solution, which uses different cache policies according...
In this paper, we have proposed a design and implementation of an AMBA based advanced DMA controller. The DMAC has 8 channels which support hardware and software triggers, linking operation and channel chaining transfer and provides three dimensions transmission by parameter sets so as to perform data block moving, data sorting and subframe extraction of various data structures. Channel arbitration...
The IEEE 1588 Standard, sometimes called PTP, specifies that PTP nodes conform to all clauses of the standard with the exception of ldquooptionalrdquo clauses and that applications that distribute only frequency do not require the measurement of the path delays (section 19.2.1, [1]). The standard doesn't provide specifications for conformance testing. Conformance testing requires the consideration...
Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers and to master hardware...
In this paper, we introduce two methods to implement clock synchronization in fiber channel. One is based on ELS (extended link service) transmission and the other is based on primitive signal transmission. Compared with the method based on ELS transmission, the primitive method is at least 20 times faster and consumes less power. Furthermore, we propose an area efficient method to implement encoding...
The complex architectures of the signal core have the bottlenecks to improve performance. The homogenous and heterogeneous multi-core architecture will be the further trends. For the job's cooperation, the synchronous behaviors are needed to keep the task achievements and, more frequently, occur in the multi-core systems. Polling and interrupt usually used as the inter-processor communication mechanisms...
This paper addresses the design issue of System-on-Chip by elevating the design abstraction levels, through a model-driven approach. It considers the standard Marte profile, which is dedicated to the Modeling and Analysis of Real-Time Embedded systems. From user-defined models, information are extracted, which serve for the analysis of the models. The adopted analysis technique relies on the synchronous...
In this paper we focus on optimizing the performance in a cluster of Simultaneous Multithreading (SMT) processors connected with a commodity interconnect (e.g. Gbit Ethernet), by applying overlapping of computation with communication. As a test case we consider the parallelized advection equation and discuss the steps that need to be followed to semantically allow overlapping to occur. We propose...
This paper presents architecture for accelerating message switch and synchronization performed in a message passing library developed on Maestro3 cluster network. Maestro3 is a high-performance cluster network that has the optimized data link layer and the capability of dynamic offload. We propose the dedicated hardware for further improvement of communication performance. In this paper, detailed...
This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables...
The synchronous programming paradigm simplifies the specification and verification of reactive systems. However, synchronous programs must be often implemented on architectures that do not follow this model of computation (like distributed systems or systems-on-a-chip). This gives rise to desynchronization techniques, which map the synchronous program to a platform without global time while preserving...
Compared with lock-based synchronization techniques, software transactional memory (STM) can significantly improve the programmability of multithreaded applications. Existing research results have demonstrated through experiments that current STM designs have slower execution speed than the locks. This paper develops a theoretical explanation for the performance difference. In particular, commit-time-locking...
FAUmachine is a virtual machine for the highly detailed simulation of standard PC hardware together with an environment. FAUmachine comes with fault injection capabilities and an automatic experiment controller facility. Due to its use of just-in-time compiler techniques, it offers good performance. This tool description introduces the new feature of FAUmachine to simulate systems deterministically...
Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable. Dependable multithreaded software will have to rely on the ability to dynamically detect non-deterministic and notoriously hard to reproduce synchronization bugs manifested through data races. Previous solutions to dynamic data race...
Conflict management is a key design dimension of hardware transactional memory (HTM) systems, and the implementation of efficient mechanisms for detection and resolution becomes critical when conflicts are not a rare event. Current designs address this problem from two opposite perspectives, namely, lazy and eager schemes. While the former approach is based on an purely optimistic view that is not...
This paper presents a method for optimising parallelisation and scheduling of task graphs containing representation of loops for implementation in heterogeneous computing systems with both software and hardware processors. The method integrates loop unrolling with task scheduling and determines the extent to which each loop should be unrolled to maximise performance, while meeting size constraints...
The design of the two-way real-time sampling circuit is completed by using TMS320VC5402 as main control chip, and two A/D-D/A converter chip TLV320AIC10 connected in master-slaver mode. The software is programmed by C in conjunction with assembly language, and is compact and efficient. The design of the module has highly practical value.
As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. Software checking approaches are attractive because they require little hardware modification and can be easily adjusted to fit different reliability and performance requirements. Unfortunately, software checking adds a significant...
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