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As computer systems increase in size and complexity, bugs become ever subtler and more difficult to detect and diagnose. A bug could exist at different layers of computer systems (e.g., applications, shared libraries, file systems, device firmware), or could be caused by the incompatibility among layers. In many cases, bugs would require a very specific combination of events to be triggered and are...
Hardware in-the-loop simulation test has the advantage of live test, digital simulation test, which can build the lifelike test environment. This kind of test can carry through repeated test of multi-sample. The key technique of the hardware in-the-loop simulation test is real-time algorithmic and communication technology. In this paper, based on reflective memory network, the design for hardware...
PWCS (Probabilistic Write / Copy-Select) is a new kind of lock-free synchronization mechanism with wait-free characteristics proposed by Nicholas Mc Guire at the 13th real-time Linux workshop, which utilizes the inherent randomness of the modern computer systems. It aims at addressing the multi-reader - single-writer problem in Linux. Based on the original label-based PWCS, we propose a hash-based...
The Open Community Runtime (OCR) is a new runtime system designed to meet the needs of extreme-scale computing. While there is growing support for the idea that future execution models will be based on dynamic tasks, there is little agreement on what else should be included. OCR minimally adds events for synchronization and relocatable data-blocks for data management to form a complete system that...
Although a variety of solutions for neuromorphic systems based on different hardware technology and software programming schemes, there has yet to be a common accepted one. Based on some recent findings in brain science, we propose a new design rule for developing a brain inspired computing system. We design and fabricate a neuromorphic chip, named ‘Tianji’ chip. A multi-chip architecture-based PCB...
A systolic serial squarer for unsigned numbers, which operates without zero words inserted between successive data words, outputs the full product and has immediate response, is presented. The systolic form is obtained by merging two adjacent multiplier cells, and the continuous operation is achieved by dividing the squaring procedure in two pipelined stages.
With the advancements in the hardware technology, it is now possible to transmit data over Ethernet at the rate of 100Mbps/1Gbps. The only limiting factor for such a high peed data transfer is the speed of the processor in the computer which does all the TCP/IP processing by using the TCP/IP software written in it. In the present system, the IR sensor used is taking 50 images of plasma per second...
For the complicated digital bus device testing, there are two approaches: dedicated bus instrument and general-purpose digital IO instrument. The dedicated bus testers provide more advanced capability including exercising the bus, injecting errors, fully characterizing specification compliance for design validating and verification phase. This paper presents a modular solution based on the general-purpose...
In this paper we examine how closely together images to be used in 3D reconstruction are captured, when acquisition is started using a software-based trigger delivered to multiple computers on a network. In addition we compare a software triggered pull system to a push system. Synchronisation is a key component in 3D reconstruction systems and can also be one of the most problematic. In a shape-from-silhouette...
The paper will present an exploratory study about the potential use of reconfigurable FPGAs in the context of Fault Tolerance Computers and digital systems for space systems. It will provide an analysis of potential applications of these new techniques, starting from classical architecture principles. The purpose of this analysis is to evaluate the feasibility of these approaches, to show the potential...
Today's embedded systems are considering cache as inherent part of their design. Unfortunately, cache memory behavior heavily depends on the past references which model a large execution history and makes WCET analysis impractical. This paper presents a novel prefetch memory mechanism that simplifies the prediction of cache hits/misses because the memory access times are independent of the execution...
We present a new technique called “Three Plane Localization” to improve the accuracy of many existing range based and range free localization schemes. The key idea is to intentionally create interference at a node by scheduling concurrent transmissions of nearby nodes. Our evaluation on the TinyNode and TelosB platforms confirmed the practicality of the technique and also underlined our theoretical...
Personal high performance computer (PHPC) requires lower cost and high performance. The Teraflops PHPC systems with special accelerator units like GPGPU have been presented, but they have difficulties in programming, compatibility and applicability. In this paper, we present HPP-PHPC, a hybrid architecture of heterogeneous processors connected by non-coherent off-chip system bus. The performance of...
The requirement that aircraft receives remote control instruction to change its mission is becoming more and more eagerly. In order to responding the control instruction rapidly, signal processor on data link terminal is studied by using pervasive computing. Accordingly, the processor system is simulated and analyzed to validate the system feasibility. Finally, the implement of prototype hardware...
The paper presents an original theory of computing infrastructure, which is quasi-holographic-element system theory. Based on this theory, a new type model that is quasi-holographic element mathematical model is formed. It reflects kinds of operation relations of number. The characteristics of the new model check and store going the same way, synchronization of compute and check, integrative store...
CodeTEST could be connected to target system with bus or 16-Channel Pod. As common connection of 16-Channel Pod, it is agility, but complexity also. This paper provides about how to use 16-Channel Pod on system of ARM. The interface is designed to be easy to implement, minimize required signals and minimize board space. The hardware assistant instrumentation tags are inserted into source code during...
Functional broadside tests were defined to avoid overtesting that may occur under structural scan-based tests. Overtesting occurs due to non-functional operation conditions created by unreachable scan-in states. Functional broadside tests were computed assuming that functional operation starts after the circuit is synchronized. We discuss the definition of functional broadside tests for the case where...
This article presents a precise synchronization algorithm based on status tracking and locking mechanism. Tracking execution state of triple computer and running state of time base counter through dual state machine not only can implement precise synchronization of TMR computer, making status synchronization precision and time-base synchronization precision below 30ns, but also save valuable interconnection...
The availability of hardware counters in computers is essential both to the applications in charge of timekeeping, and those in need of accurate timestamping. Newer counters are now supported by open source operating systems, but the access interfaces are unnecessarily restricted, and in particular fail to satisfy the needs of feed-forward based synchronization algorithms. In this paper we present...
In this paper, a residual frequency offset (RFO) synchronization scheme using a simplified coordinate rotation digital computer (CORDIC) algorithm is proposed for orthogonal frequency division multiplexing (OFDM) systems. The RFO synchronization scheme using a conventional CORDIC algorithm uses the vector-mode CORDIC for RFO estimation, and the rotation-mode CORDIC for RFO compensation. The proposed...
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