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Arch MDE for "Architecture-centric Model Driven Engineering" is an approach that addresses the development and the formal verification of real time software architecture. It borrows concepts from Model Driven Engineering (MDE)and software architecture for the automatic generation of a network of timed automata, in accordance with blackboard architectural style. The generation is based on...
Nowadays, most complex embedded systems follow a distributed approach in which a network interconnects potentially large numbers of nodes. One technology that is being increasingly used is switched Ethernet, but real-time variants of this protocol typically limit scalability. In this paper, we focus on the scalability of the Flexible Time Triggered communication over Switched Ethernet (FTT-SE), which...
We propose in this paper a new modular framework to specify real time embedded systems. This model allows to express the behavior of a system through a specification that composes time Petri nets with algebraic operators. We provide its formal semantics and show how it can be used to capture the behavior of many complex real time systems.
A fully digital FPGA-based high count-rate coincidence system has been developed for TOF and non-TOF PET cameras. Using hybrid method combining AND-logic and Time-mark technology can gain both excellent timing resolution and high processing speed. In this hybrid architecture, every gamma event is synchronized by a 125 MHz system clock and generating a trigger associated with a time-mark given by an...
Multicast parametric synchronous sampling (MPASS) architecture for real-time processing of optical signals based on parametric processes is reviewed. The processor uses parametric gates to obtain multiple sub-rate outputs. Operating principle and first demonstrations are described.
In this paper we introduce a distributed emulator for a pedestrian tracking system using active tags that is currently being developed by the authors. The emulator works on StarBED which is a network testbed consisting of hundreds of PCs connected to each other by Ethernet. The three major components of the emulator (the processor emulator of the active tag micro-controller, RUNE, and QOMET) are all...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
Expected growth in use and implementation of wireless sensor networks (WSNs) in different environments and for different applications creates new security challenges. In WSNs, a malicious node may initiate incorrect path information, change the contents of data packets, and even hijack one or more genuine network nodes. As the network reliability completely depends on individual nodespsila presence...
Video-streaming can now be offered on third-generation (3G) mobile networks. Most research efforts have focused on video download. This paper presents a detailed study of challenges faced for successfully deploying applications requiring life video upload. Both subjective and objective qualities as well as the effects of mobility are analyzed on real 3G networks. Consequently, video profiles are identified...
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