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In a recently published paper, a novel ap-proach for blind feedback synchronization of the symbol tim-ing has been proposed. In order to avoid any jitter floor irre-spective of the selected modulation scheme, a filter with very particular properties has been developed and placed in par-allel to the receiver matched filter. Nevertheless, the jitter performance of this method degrades in case the carrier...
An all-digital fast frequency acquisition full-rate clock and data recovery (CDR) circuit for USB 2.0 applications without a reference clock is presented in this paper. The proposed digitally controlled oscillator (DCO) with an embedded time-to-digital converter (TDC) can recover the frequency of the synchronous data pattern in a very short time. In addition, the whole frequency acquisition can be...
Clock recovery is a key ingredient in any video system. This paper presents a novel clock recovery structure that utilizes a new digital loop that augments the well-known fractional phase locked loop. This clock data recovery achieves the desired functionality for any video system with very small jitter attributes and with multiple output phases without using off-chip components. The proposed design...
Recently, structural health monitoring technologies draw keen attention for sustaining large structures. In this paper, a smart sensor network consisting of intelligent sensor nodes with an accurate time synchronization mechanism for structural health monitoring is proposed. Using a prototype system, extensive tests have been conducted to ensure its performance. The proposed sensor network could achieve...
Clock signal impact on ADC characteristics in ADE-modules of telecommunication systems of transmission is being investigated. Qualitative characteristics and analytical dependences are obtained. Phase instability of clock signal (PICS) is accepted as the generalized characteristic which evaluates the quality of clock signal of ADC and noises impact. Jitter value of clock signal is used for quantitative...
More and more advanced features such as adaptive cruise control, collision avoidance, and stability control are being implemented in vehicles. These features are usually implemented as distributed CAN (controller area network) systems right now. In a CAN system, normally there is no clock synchronization among the ECU (electronic control unit) nodes connected by the CAN bus. Without synchronization,...
IEEE 802.1AS is being developed in the 802.1 working group as part of a set of standards for audio/video bridging (AVB). AVB networks will carry time-sensitive, high-quality, audio/video traffic, and IEEE 802.1AS will provide synchronization for these networks and ensure that the jitter, wander, and synchronization requirements for the time-sensitive traffic can be met. IEEE 802.1AS includes an IEEE...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
With respect to the European Action Plan for Energy Efficiency, AMR is an intensively discussed subject. One major aspect concerning AMR via power line communications (PLC) is the synchronization of communication systems. Common synchronization techniques are limited due to omnipresent, intensive and permanent disturbance, frequency or timing restrictions. In this paper, we analyze a synchronization...
The interdependence of periodic signals phase noise and front time signal shaking are being studied to develop the approaches to found mathematical model of phase noise power spectral constituents (time signals jitter). A basic analysis is made on the example of periodic test signal. The physical matter of phase shaking power is examined and phase noise power mathematical description is obtained in...
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