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In this paper a node localization algorithm for estimating unknown node positions in wireless sensor networks is presented. The proposed algorithm is based on the distributed clustering of anchor-free nodes. In the absence of anchor nodes, clusters of these sensors are formed and relevant angular and distance measurements are taken. This is followed by two phases of nodes synchronization, in which...
This paper proposes a dissimilar four-redundancy Electrical Load Management Center (ELMC) to meet the reliability requirement of More/All Electric Aircraft (MEA/AEA), which is able to effectively eliminate the common mode fault of the redundant system. The CPUs of the dissimilar four-redundancy ELMC are composed of two DSP and two FPGA, which can be considered as the hardware dissimilar redundancy...
Network-based clock synchronization is an important prerequisite for many application areas and more and more required for the factory floor for network arbitration, control, and monitoring. Limitations of existing clock synchronization protocols are that they either support high redundancy and robustness or high precision. This paper presents an approach to integrate slave-side robustness into high...
Reliability is one of the most important target in airplane designing, the redundancy technology is universally used in servo-actuator system of civil aircraft's Fly-by-Wire System (FBWS). In order to attain a high reliability, firstly the system structure is designed and redundancy allocation is given, accordingly the redundant management strategy and realization are described in detail. Based on...
Reducing power consumption to extend network lifetime with limited energy resource is one of the most important challenges in industrial wireless networks. WIA-PA network requires limited energy resource, adapts dynamic surroundings and keeps the reliability of the network. Aiming at low power consumption and cost, this paper introduces the wireless networks for industrial automation on framework,...
Redundancy can improve the availability of components in service-oriented systems. However, predicting and quantifying the effects of different redundancy strategies can be a complex task. In our work, we have taken an architecture based approach to the modeling, predicting and monitoring of properties in distributed software systems.This paper proposes redundancy strategies for service-oriented systems...
The Reliable Server Pooling (RSerPool) architecture is the IETF's new standard for a lightweight server redundancy and session failover framework to support availability-critical applications. RSerPool combines the ideas from different research areas into a single, resource-efficient and unified architecture. Server pools are maintained by redundant management components, which are called registrars...
The specifications of the protocols supporting mobility - MIPv6, NEMO - centralize their key functionalities on the home agent, which represents a single point of failure. In the context of the French research project REMORA, we have developed a solution to make home agent-based mobility protocols more reliable against the home agent failures. This paper presents the design, the implementation and...
In this paper, we propose a new control method to cover ldquoholesrdquo in wireless sensor networks. Many applications often face the problem of holes when some sensor nodes are disabled from the collaboration due to their failures and misbehavior. These holes may occur dynamically, and such a problem cannot be solved completely by simply deploying more redundant sensors. With synchronization around...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
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