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A 120 MHz fractional-N frequency synthesizer was implemented in a standard 0.18mum CMOS process with an on-chip multiphase voltage-controlled oscillator (VCO). The proposed architecture uses multiphase outputs of the VCO to decrease quantization noise from the sigma-delta (SigmaDelta) modulator. Results show the decrease in quantization noise from the 4th order SigmaDelta is 6dB for every two fold...
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