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This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement...
An 11-bit 20-MS/s algorithmic analog-to-digital converter (ADC) based on a dynamic biasing technique is proposed. A dynamic biasing technique is employed to an operational transconductance amplifier (OTA) for power reduction in sub-conversion stages. Besides, a distinct sampling clock scheme is taken to pre-amplifier for reducing aperture time errors. The prototype ADC is fabricated in a 65 nm 1P6M...
An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on binary successive approximation algorithm (SA) using a capacitive ladder. The semi-close loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. One bit redundancy is implemented to compensate the process variation of parasitic and the MOM capacitance. Fabricated...
An on-chip circuit to measure static phase offset between a reference signal and the feedback signal of a PLL (phase-locked loop) is designed using only digital elements. It is demonstrated in a 65 nm, 1.0 V CMOS technology. It has a measured resolution of 2 ps and a range of more than +/-100 ps of phase offset and, and consumes 3 mW of power at 1 GHz. It uses an on-chip calibration referred to the...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
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