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Based on the application of high-speed, high-resolution A/D converter, this paper describes the design and implementation of a novel high-speed comparator. The comparator uses the high-speed, transmission delay stability technology, the auto-zero technology, and the cascade technology in order for the comparator to have the high-speed, high-resolution, transmission delay stability features. Its performances...
In this paper, a dynamic timing control technique employing a time-borrowing flip-flop with a time-borrowing detection and a clock shifter is presented to prevent timing errors of a system with a minimized performance penalty. The proposed flip-flop allows time borrowing during a time-borrowing window (TBW) on critical paths and generates a time-borrowing detection signal used by the clock shifter...
An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on binary successive approximation algorithm (SA) using a capacitive ladder. The semi-close loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. One bit redundancy is implemented to compensate the process variation of parasitic and the MOM capacitance. Fabricated...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
This paper presents the design and measured results of a novel static frequency divider that operates at a frequency 28% higher than a current-mode logic (CML) divider. The frequency divider was designed and implemented in IBM's 0.5 mum SiGe BiCMOS technology with an fT of 47 GHz. The divider adds an additional delayed clock phase to a conventional CML- based divider. Measured results show operation...
In this paper self-timed circuits for synchronization at bit level are described. For a high functional throughput rate a circuit granularity of two full additions per handshake cycle will be proposed. Functionality of this concept is shown for a 1,5??m- and a 0,8??m-CMOS-technology. Technology migration is possible without any change of circuit design. Device performance enhancement is completely...
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