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An on-chip 45nm test platform that directly monitors circuit performance degradation during dynamic operation is demonstrated. In contrast to traditional ring-oscillator (RO) based frequency measurements, it utilizes a Time-to-Digital Converter (TDC) with 2ps resolution to efficiently monitor circuit delay change on-the-fly. This new technique allows the capability of measuring signal edge degradation...
PLLs generate clocks for the core logic in many ICs. As frequencies increase above 500 MHz, jitter and duty cycle error become significant and more likely to affect logic function. Measuring these parameters off-chip can be too expensive or impractical. This paper describes how a PLL BIST is being implemented in production ICs to test jitter, duty cycle, phase delay, frequency ratio, and lock time...
Small delay defect (SDD) testing is expected to become more prevalent as technology nodes continue to shrink and design frequencies continue to increase. In this paper, we critically examine previously published methods for evaluating SDD coverage and identify their shortcomings as an accurate and practical coverage metric. We propose an accurate method for measuring the coverage of small delay defects...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
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