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Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a...
This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
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