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Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
For speedy robust object recognition, our model builds on Serre’s standard model and modifies it by additional biological characteristics, such as introducing the manner of neuron firing, feature localization, and merging unit features in the higher layers. According to the four-layer architecture of standard model, we first apply Gabor filters on a higher intermediate frequency band of original image,...
Straight line programs in which array elements can be referenced and set are considered. Two programs are equivalent if they compute the same expression as a function of the inputs. Testing the equivalence of programs with arrays is shown to be NP-complete, while programs without arrays can be tested for equivalence in linear time. Equivalence testing takes polynomial time when programs have either...
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