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A negative-bias-temperature-instability (NBTI) monitor subcircuit is presented and implemented in 65-nm CMOS technology. The subcircuit can be incorporated in various analog circuit blocks subject to different variability, stress, and aging histories. For an amplifier block, the NBTI monitor is a linear sensor, and sensing is provided as variation of the amplifier gain in response to NBTI-induced...
A dual displacement measurement meter applied as a compensatory device for spindle thermal growth compensation, it can reduce the measurement error dramatically from single measurement device. The result matches the laser inspection report, which is an external direct checking device and been considered as one of the best checking device of spindle thermal growth. However, the non-flat surface of...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
A 53 dB gain limiting amplifier for OC-192 and 10 GbE applications is developed in a 50 GHz fT SiGe SOI complimentary bipolar process, and has 5 mV pk-pk sensitivity, 1.25 V pk-pk maximum input signal, 14 ps (20/80%) rise/fall times and 450 mV pk-pk output into matched differential 50 Ohm loads, consuming 430 mW on a 3.3 V supply. Input Cherry-Hooper gain stages limit the -3 dB bandwidth to 11 GHz...
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