The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In recent years, the RapidSmith CAD tool [1] has been used with ISE to create custom CAD tools targeting Xilinx FPGAs. This tool flow was based on the Xilinx Design Language (XDL), a human-readable representation of a netlist that contains placement and routing information. The XDL interface also provided device representation files (XDLRC files), detailing the available resources of a given FPGA...
As IPv6 has much larger address space than IPv4, understanding the characteristics of IPv6 prefixes is of great benefit to guide the efficient IPv6 routing cache design. In this paper, we make a first-ever analysis of prefix-level characteristics in IPv6 world. We first investigate the assignment and activity of IPv6 prefixes. Then we characterize the traffic and packet distribution across prefixes...
Partial reconfiguration is possible to deliver virtually unlimited hardware resources since it enables dynamic allocation and de-allocation of tasks onto a reconfigurable architecture, while the rest tasks continue to operate. However, in order to benefit from this flexibility, partial reconfiguration has to be appropriately applied. Among others, the placement of partial configuration data is a critical...
Geiselmann and Steinwandt proposed an ASIC based hardware design “YASD” for the sieving step in the number field sieve (NFS) method of integer factorization in 2004. The design is attractive since its regular structure seems suitable for implementation, however, performance valuation for 1024-bit integers has not been provided. This paper firstly evaluates the performance of YASD for 1024-bit integers...
Cluster technology has witnessed a tremendous inception in computing world. The technique integrates the standard computing resources to generate more processing power and other hardware strengths. The collection of interconnected stand-alone computers ensures high availability, increased throughput, scalability and improved performance. We have developed a dynamic cluster based approach for high...
This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary...
When implementing some applications in multi-computer systems, broadcast operation is a necessity for efficient communication. Several broadcast algorithms have been proposed in the literature for hypercube networks. In this paper, we evaluate the performance of broadcast routing algorithms for hypercube networks, and propose a new approach by reducing the number of steps required to perform.
Broadcast is among the most primitive collective communication operations of any interconnection network. Broadcast algorithms for the mesh topology have been widely reported in the literature. However, most existing algorithms have been studied in one-port and within limited conditions, such as light traffic loads. In contrast, this study simulates the broadcast operations, taking into account a...
Self, partial and dynamical reconfiguration, in both its 1D and 2D paradigms, gives the possibility of enhancing the flexibility of a reconfigurable system. It is a powerful approach but, at the same time, causes a significant increase in the complexity of system creation and management. The 1D paradigm allows the dynamical reconfiguration of columns spanning the whole device vertically; the 2D paradigm,...
Multicomputers can be effectively used for interactive graphics rendering only if there are mechanisms available to rapidly composite and transfer images to an external display device. One method for achieving the necessary bandwidth for this operation is to provide multiple high-bandwidth ports into a frame buffer. In this paper, we evaluate the design space of a multiport frame buffer design for...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.