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Accurate diagnosis of open defects is key to identifying process problems and achieving fast yield improvement. Current diagnosis methodologies for interconnect full open defects have demonstrated their efficiency, assuming that the defective line voltage is mainly determined by neighboring lines and downstream transistor parasitic capacitances. However, the continuous reduction of oxide thickness...
In this paper we present a method to identify don't care locations in a fully specified set of vectors, considering both fault propagation path and fault activation path. We exploit the identified X bits to convert the original vector to low power vector by dictionary based approach to minimize both dynamic and runtime leakage power. The dynamic power as well as the runtime leakage power depends on...
Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open- via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation...
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