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A new generation of Power MOSFET technology has been introduced. The devices are manufactured in a standard 0.35??m CMOS production line with only few process modules being adapted for the requirements of vertical power transistors with a 2x improvement in Figure of Merit (FOM). This improvement results mainly from the reduction in Miller capacitance.
A detailed TCAD analysis of a low-Cgd high-power RF MOSFET incorporating a 0.25 mum sidewall gate is presented. A novel conductive plate is placed in the vicinity of the gate poly as well as underneath the gate interconnects to provide a complete shield of the gate from the influence of drain potential. The fabricated vertical DMOS device exhibits a Id(sat) = 750 muA/mum and an extrinsic transconductance...
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